The present invention relates generally to scan testing of digital circuits and more particularly, to debugging the scan chains used in scan testing.
Recent years have seen tremendous advancement in the fields of electronic devices, electronic circuit integration and printed circuit boards (PCB). Devices that contained ICs with a few hundred transistors a few decades ago, now include millions of transistors. These advancements have led to an increase in circuit density and considerable miniaturization in devices. However, miniaturization of devices has made circuit testing difficult. Traditional testing techniques, such as ‘bed of nails’ testing have not been able to provide accurate test results and proven to be expensive. Further, such test methodologies fail when used to test devices with multilayered PCBs, pitched packages, and double-sided surface mount boards.
To overcome the above-stated limitations of traditional test methodologies, scan testing has been developed. Scan testing entails shifting scan test vectors into integrated circuits (IC) through scan cells that are organized as one or more shift registers. The scan test vectors are applied to the internal logic of the ICs and the corresponding scan-out vectors are saved. Thereafter, the scan-out vectors are compared with ideal responses to determine whether the IC has any faults. An extension of scan testing involves providing compressed scan test data during scan testing. Test data compression capitalizes on an aspect of scan testing in which only a small percentage of scan cells need to be assigned specific values. The remaining scan cells can hold random values and are considered as ‘don't care’. Thus, shifting-in and shifting-out fewer test values reduces the test data and test time.
Scan testing with test data compression entails organizing the scan cells as multiple scan chains, each of a shorter length, as compared to the scan chain lengths in customary scan testing without data compression. The scan chains are then driven by an on-chip decompressor, which loads the multiple scan chains simultaneously by decompressing the test data delivered to it. Thereafter, the IC is tested using the test data and responses of the IC to the test data are shifted out of the scan chains as response data. The response data is then compressed by an on-chip compressor and provided to an external comparator for comparing the response data with the ideal response data to determine whether the IC contains any faults.
Although the above technique provides the advantages of test time and test data reduction, this technique complicates the debug process required to detect and locate scan chain failures that are primarily due to silicon level failures. The existence of compressor and de-compressor logic prevents deterministic control and observation of patterns, which in turn leads to complication in the creation of custom chain patterns for debugging purposes. For example, it is quite challenging to generate test patterns with reduced activity for ruling out noise and IR drop issues. Thus, it would be beneficial to provide more controllability with regard to scan chain selection during debugging and more observability with regard to scan response vector observation, thereby facilitating the scan chain debug process and expediting the isolation of the faulty scan chains and failing scan cells.